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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM62110/D
32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker
The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check. This device has increased output drive capability supported by multiple power pins. In addition, the output levels can be either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power supply. The device has both asynchronous and synchronous inputs. Asynchronous inputs include the processor output enable (POE), system output enable (SOE), and the clock (K). The address (A0 - A14) and chip enable (E1 and E2) inputs are synchronous and are registered on the falling edge of K. Write enable (W), processor input enable (PIE) and system input enable (SIE) are registered on the rising edge of K. Writes to the RAM are self-timed. All data inputs/outputs, PDQ0 - PDQ7, SDQ0 - SDQ7, PDQP, and SDQP have input data registers triggered by the rising edge of the clock. These pins also have three-state output latches which are transparent during the high level of the clock and latched during the low level of the clock. This device has a special feature which allows data to be passed through the RAM between the system and processor ports in either direction. This streaming is accomplished by latching in data from one port and asynchronously output enabling the other port. It is also possible to write to the RAM while streaming. Additional power supply pins have been utilized for maximum performance. The output buffer power (VCCQ) and ground pins (VSSQ) are electrically isolated from VSS and VCC, and supply power and ground only to the output buffers. This allows connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels are chosen, the output buffer impedance in the ``high'' state is approximately equal to the impedance in the ``low'' state thereby allowing simplified transmission line terminations. The MCM62110 is available in a 52-pin plastic leaded chip carrier (PLCC). This device is ideally suited for pipelined systems and systems with multiple data buses and multiprocessing systems, where a local processor has a bus isolated from a common system bus. * Single 5 V 10% Power Supply * Choice of 5 V or 3.3 V 10% Power Supplies for Output Level Compatibility * Fast Access and Cycle Times: 15/17/20 ns Max * Self-Timed Write Cycles * Clock Controlled Output Latches * Address, Chip Enable, and Data Input Registers * Common Data Inputs and Data Outputs * Dual I/O for Separate Processor and Memory Buses * Separate Output Enable Controlled Three-State Outputs * Odd Parity Checker During Reads * Open Drain Output on Data Parity Error (DPE) Allowing Wire-ORing of Outputs * High Output Drive Capability: 85 pF/Output at Rated Access Time * High Board Density 52 Lead PLCC Package * Active High and Low Chip Enables for Easy Memory Depth Expansion * Can be used as Separate I/O x9
MCM62110
FN PACKAGE PLASTIC CASE 778-02
PIN ASSIGNMENT
SIE PIE SOE POE W K VCC VSS DPE A6 A4 A2 A0 E2 E1 PDQ7 SDQ7 VSSQ PDQ5 SDQ5 VCCQ PDQ3 SDQ3 VSSQ PDQ1 SDQ1 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A14 A13 A12 A11 A10 VSS VCC A9 A8 A7 A5 A3 A1 PDQP SDQP VSSQ PDQ6 SDQ6 VCCQ PDQ4 SDQ4 PDQ2 SDQ2 VSSQ PDQ0 SDQ0
PIN NAMES
A0 - A14 . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input W . . . . . . . . . . . . . . . . . . . . . . . Write Enable E1 . . . . . . . . . . . . . Active Low Chip Enable E2 . . . . . . . . . . . . . Active High Chip Enable PIE . . . . . . . . . . . . . Processor Input Enable SIE . . . . . . . . . . . . . . . System Input Enable POE . . . . . . . . . . Processor Output Enable SOE . . . . . . . . . . . . . System Output Enable DPE . . . . . . . . . . . . . . . . . . Data Parity Error PDQ0 - PDQ7 . . . . . . . Processor Data I/O PDQP . . . . . . . . . . . Processor Data Parity SDQ0 - SDQ7 . . . . . . . . . System Data I/O SDQP . . . . . . . . . . . . . System Data Parity VCC . . . . . . . . . . . . . . . + 5 V Power Supply VCCQ . . . . . . Output Buffer Power Supply VSSQ . . . . . . . . . . . . Output Buffer Ground VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground All power supply and ground pins must be connected for proper operation of the device. VCC VCCQ at all times including power up.
REV 3 5/95
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM62110 1
BLOCK DIAGRAM
DPE
PDQ0 - PDQ7, PDQP
POE
K
DATA REGISTER DATA REGISTER
9 DATA LATCH CONTROL DATA REGISTER SOE SDQ0 - SDQ7, SDQP Output High-Z Data Out Data Out High-Z High-Z High-Z Data In Stream Data Data In Stream Data Data In High-Z Stream High-Z Data In Data In DPE Parity Out Parity Out Parity Out 1 1 1 1 1 1 1 1 1 1 1 1 1 2, 5 2, 6 2 2, 7 2, 7 2, 7 2, 7 5 2, 8 2, 8 2, 8 2, 8
A0 - A14 32K x 9 ARRAY REGISTER
PARITY CHECK
WRITE DRIVER
9
W E1 E2 PIE SIE
SENSE AMPLIFIER
DATA LATCH
9 SDQ0 - SDQ7, SDQP
FUNCTIONAL TRUTH TABLE (See Notes 1 and 2)
W 1 1 1 1 X 0 0 0 0 1 1 0 X X X X PIE 1 1 1 X 0 0 1 0 1 0 1 1 0 0 1 1 SIE 1 1 1 X 0 1 0 1 0 1 0 1 1 1 0 0 POE 0 1 0 1 X 1 1 1 0 1 0 X 0 0 0 1 SOE 1 0 0 1 X 1 1 0 1 0 1 X 0 1 0 0 Mode Read Read Read Read N/A Write Write Write Write N/A N/A N/A N/A N/A N/A N/A Memory Subsystem Cycle Processor Read Copy Back Dual Bus Read NOP NOP Processor Write Hit Allocate Write Through Allocate With Stream Cache Inhibit Write Cache Inhibit Read NOP Invalid Invalid Invalid Invalid PDQ0 - PDQ7, PDQP Output Data Out High-Z Data Out High-Z High-Z Data In High-Z Data In Stream Data Data In Stream Data High-Z Data In Data In Stream High-Z Notes 3, 4 3, 4 3, 4
NOTES: 1. A `0' represents an input voltage VIL and a `1' represents an input voltage VIH. All inputs must satisfy the specified setup and hold times for the falling or rising edge of K. Some entries in this truth table represent latched values. This table assumes that the chip is selected (i.e., E1 = 0 and E2 = 1) and VCC current is equal to ICCA. If this is not true, the chip will be in standby mode, the VCC current will equal ISB1 or ISB2 DPE will default to 1 and all RAM outputs will be in High-Z. Other possible combinations of control inputs not covered by this note or the table above are not supported and the RAM's behavior is not specified. 2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don't care, and the corresponding outputs are High-Z. 3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM. 4. DPE is registered on the rising edge of K at the beginning of the following clock cycle 5. No RAM cycle is performed. 6. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 - PDQ7 and PDQP or SDQ0 - SDQ7 and SPDQ), and written into the RAM. 7. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other I/O port. 8. Data contention will occur.
MCM62110 2
MOTOROLA FAST SRAM
PARITY CHECKER
Parity Scheme E1 = VIH and/or E2 = VIL RAMP = RAM0 RAM1 . . . RAM7 RAMP RAM0 RAM1 . . . RAM7 DPE 1 1 0
NOTE: RAMP, RAM0, RAM1 . . . , refer to the data that is present on the RAMs internal bus, not necessarily data that resides in the RAM array. DPE is always delayed one clock, and is registered on the rising edge of K at the beginning of the following clock cycle (see AC CHARACTERISTICS).
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = VSSQ = 0 V)
Rating Power Supply Voltage Relative to VSS/VSSQ for Any Pin Except VCC and VCCQ Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 1.2 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM62110 3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, VCCQ = 5.0 V or 3.3 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = VSSQ = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Output Buffer Supply Voltage (5.0 V TTL Compatible) (3.3 V 50 Compatible) Input High Voltage Input Low Voltage * VIL (min) = - 3.0 V ac (pulse width 20 ns) Symbol VCC VCCQ VIH VIL Min 4.5 4.5 3.0 2.2 - 0.5* Max 5.5 5.5 3.6 VCC + 0.3 0.8 Unit V V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (POE, SOE = VIH) AC Supply Current (All Inputs = VIL or VIH,VIL = 0.0 V and VIH 3.0 V, Iout = 0 mA, Cycle Time tKHKH min) MCM62110-15: tKHKH = 15 ns MCM62110-17: tKHKH = 17 ns MCM62110-20: tKHKH = 20 ns TTL Standby Current (VCC = Max, E1 = VIH or E2 = VIL) CMOS Standby Current (VCC = Max, f = 0 MHz, E1 = VIH or E2 = VIL, Vin VSS + 0.2 V or VCC - 0.2 V) Output Low Voltage (IOL = + 8.0 mA, DPE: IOL = + 23.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA -- -- -- ISB1 ISB2 VOL VOH -- -- -- 2.4 190 190 190 40 30 0.4 -- mA mA V V Min -- -- Max 1.0 1.0 Unit A A mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (All Pins Except I/Os) Input/Output Capacitance (PDQ0 - PDQ7, SDQ0 - SDQ7, PDQP, SDQP) Data Parity Error Output Capacitance (DPE) Symbol Cin Cout Cout(DPE) Typ 2 6 6 Max 3 7 7 Unit pF pF pF
AC SPEC LOADS
+5V RL = 50 DQ Z0 = 50 VL = 1.5 V 480 DQ 255 5 pF DPE
+5V 200
50 pF
Figure 1A
Figure 1B
Figure 1C
MCM62110 4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, VCCQ = 5.0 V or 3.3 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE (See Note 1)
MCM62110-15 Parameter Read Cycle Time Clock High to Clock High Clock Low Pulse Width Clock High Pulse Width Clock High to DPE Valid Clock High to Output Valid Clock (K) High to Output Low Z After Write Output Hold from Clock High Clock High to Q High-Z (E1 or E2 = False) Setup TImes: A W E1, E2 PIE SIE POE SOE A W E1, E2 PIE SIE POE SOE Symbol tKHKH tKLKH tKHKL tKHDPEV tKHQV tKHQX1 tKHQX2 tKHQZ tAVKL tWHKH tEVKL tPIEHKH tSIEHKH tPOEVKH tSOEVKH tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHPOEX tKHSOEX tPOEHQZ tSOEHQZ tPOEHQX tSOEHQX tPOELQX tSOELQX tPOELQV tSOELQV Min 15 5 7 -- -- 8 5 -- 2.5 Max -- -- -- 7 7 -- -- 8 -- MCM62110-17 Min 17 5 7 -- -- 8 5 -- 2.5 Max -- -- -- 8 7.5 -- -- 9 -- MCM62110-20 Min 20 5 7 -- -- 8 5 -- 2.5 Max -- -- -- 10 10 -- -- 10 -- Unit ns ns ns ns ns ns ns ns ns 4, 6 6 5 4, 3 Notes 1, 2
7 7 2 -- 2 -- 2 -- ns
Hold Times:
7 7 0 5 0 -- 8 -- -- 5 0 5 0 -- 9 -- -- 6 0 5 0 -- 9 -- -- 8 ns ns ns ns 6 6 6
Output Enable High to Q High-Z Output Hold from Output Enable High Output Enable Low to Q Active Output Enable Low to Output Valid
NOTES: 1. A read is defined by W high for the setup and hold times. 2. All read cycle timing is referenced from K, SOE, or POE. 3. Access time is controlled by tKLQV if the clock low pulse width is less than (tKLQV-tKHQV); otherwise it is controlled by KHQV. 4. K must be at a high level for outputs to transition. 5. DPE is valid exactly one clock cycle after the output data is valid. 6. Transition is measured 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for a given device. 7. These read cycle timings are used to guarantee proper parity operation only.
MOTOROLA FAST SRAM
MCM62110 5
READ CYCLE (See Notes)
tKHKH tKHKL
tKLKH K tKLAX tAVKL A0 - A14 An
An + 1
An + 2
E1 tKLEX E2 tKHPIEX PIE tKHSIEX SIE tKHWX W tPOEVKH tKHPOEX POE tPOELQV tPOELQX SOE tPOEHQZ tPOEHQX tSOELQV PDQ0 - PDQ7, PDQP tKHQV SDQ0 - SDQ7, SDQP tKHDPEV DPE DPE - 2 DPEn - 1 Qn tKHQX2 DPEn Qn tKHQZ tKHQX1 tWHKH tSIEHKH tPIEHKH tEVKL
NOTES: 1. DPE is valid exactly one clock cycle after the output data is valid.
MCM62110 6
MOTOROLA FAST SRAM
WRITE CYCLE (See Note 1)
MCM62110-15 Parameter Write Cycle Times Clock Low Pulse Width Clock High Pulse Width Clock High to Output High-Z (W = VIL and SIE = PIE = VIH) Setup Times: A W E1, E2 PIE SIE SDQ0 - SDQ7, SDQP, PDQ0 - PDQ7, PDQP A W E1, E2 PIE SIE SDQ0 - SDQ7, SDQP, PDQ0 - PDQ7, PDQP Symbol tKHKH tKLKH tKHKL tKHQZ tAVKL tWLKH tEVKL tPIEVKH tSIEVKH tDVKH tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHDX tKHQV Min 15 5 7 -- 2.5 Max -- -- -- 8 -- MCM62110-17 Min 17 5 7 -- 2.5 Max -- -- -- 9 -- MCM62110-20 Min 20 5 7 -- 2.5 Max -- -- -- 10 -- Unit ns ns ns ns ns 3, 4 Notes 1, 2
Hold Times:
2
--
2
--
2
--
ns
Write with Streaming (PIE = SOE = VIL or SIE = POE = VIL) Clock High to Output Valid Output Enable High to Q High-Z Output Hold from Output Enable High Output Enable Low to Q Active Output Enable Low to Output Valid
--
7
--
7.5
--
8
ns
5
tPOEHQZ tSOEHQZ tPOEHQX tSOEHQX tPOELQX tSOELQX tPOELQV tSOELQV
0 5 0 --
8 -- -- 5
0 5 0 --
9 -- -- 6
0 5 0 --
9 -- -- 8
ns ns ns ns
6
6
NOTES: 1. A write is performed with W = VIL, E1 = VIL, E2 = VIH for the specified setup and hold times and either PIE = VIL or SIE = VIL. If both PIE = VIL and SIE = VIL or PIE = VIH and SIE = VIH, then this is treated like a NOP and no write is performed. 2. All write cycle timings are referenced from K. 3. K must be at a high level for the outputs to transition. 4. Transition is measured 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX for a given device. 5. A write with streaming is defined as a write cycle which writes data from one data bus to the array and outputs the same data onto the other data bus. 6. Transition is measured 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tKHQZ is less than tKHQX, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for a given device.
MOTOROLA FAST SRAM
MCM62110 7
WRITE THROUGH -- READ -- WRITE (See Note)
tKHKH tKLKH K tKLAX A0 - A14 An tAVKL An + 1 An + 2 tKHKL
E1 tKLEX E2 tKHPIEX PIE tKHSIEX tSIEVKH SIE tKHWX W tWLKH tWHKH tKHWX tSIEHKH tKHSIEX tPIEVKH tPIEHKH tKHPIEX tEVKL
POE tPOEHQZ SOE tDVKH tKHDX tSOELQV PDQ0 - PDQ7, PDQP Qn - 1 Dn tKHQV SDQ0 - SDQ7, SDQP Qn - 1 tKHDPEV DPE DPEn - 2 DPEn - 1 Qn (STREAMED) tPOEHQX tSOEHQZ tPOELQV tSOEHQX tKHDX tPOEHQZ tDVKH Qn +1 Dn + 2
tPOELQX
NOTE: DPE is valid exactly one clock cycle after the output data is written.
MCM62110 8
MOTOROLA FAST SRAM
STREAM CYCLE (See Note 1)
MCM62110-15 Parameter Stream Cycle Time Clock Low Pulse Width Clock High Pulse Width Stream Access Time Setup Times: A W E1, E2 PIE SIE SDQ0 - SDQ7, SDQP, PDQ0 - PDQ7, PDQP A W E1, E2 PIE SIE SDQ0 - SDQ7, SDQP, PDQ0 - PDQ7, PDQP Symbol tKHKH tKLKH tKHKL tKHQV tAVKL tWHKH tEVKL tPIEVKH tSIEVKH tDVKH tKLAX tKHWX tKLEX tKHPIEX tKHSIEX tKHDX tPOEHQZ tSOEHQZ tPOELQX tSOELQX tPOELQV tSOELQV Min 15 5 7 -- 2.5 Max -- -- -- 7 -- MCM62110-17 Min 17 5 7 -- 2.5 Max -- -- -- 7.5 -- MCM62110-20 Min 20 5 7 -- 2.5 Max -- -- -- 8 -- Unit ns ns ns ns ns Notes 1, 2
Hold Times:
2
--
2
--
2
--
ns
Output Enable High to Q High-Z Output Enable Low to Q Active Output Enable Low to Output Valid
0 0 --
8 -- 5
0 0 --
9 -- 6
0 0 --
9 -- 8
ns ns ns
3 3
NOTES: 1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus. 2. All stream cycle timing is referenced from K. 3. Transition is measured 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At any given voltage and temperature, tPOEHQZ is less than tPOELQX, tSOEHQZ is less than tSOELQX, and tKHQZ is less than tKHQX for a given device.
MOTOROLA FAST SRAM
MCM62110 9
STREAM CYCLE (See Note)
tKHKH tKLKH K tKLAX tAVKL A0 - A14 An An + 1 An + 2 tKHKL
E1 tKLEX E2 tKHPIEX PIE tKHSIEX SIE tWHKH W tKHWX tSIEVKH tPIEVKH tEVKL
POE tPOEHQZ SOE tDVKH PDQ0 - PDQ7, PDQP Qn - 1 Dn tKHQV SDQ0 - SDQ7, SDQP Qn - 1 tKHDPEV DPE DPEn - 2 DPEn - 1 Qn (STREAMED) Dn + 1 tSOEHQZ tKHDX tKHQV Qn + 1 (STREAMED)
NOTE: DPE is valid exactly one clock cycle after the output data is valid.
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
62110
FN
XX
Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns) Package (FN = PLCC)
Full Part Numbers -- MCM62110FN15
MCM62110FN17
MCM62110FN20
MCM62110 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE 52-LEAD PLCC CASE 778-02
B -NY BRK D -L52 LEADS ACTUAL -MW D V A Z R 0.007 (0.180)
M
0.007 (0.180) U
M
T L -M
M
S
N
S
0.007 (0.180)
T L -M
S
N
S
Z
(NOTE 1) 52
1
X VIEW D-D 0.007 (0.180)
M
G1 0.010 (0.250)
S
T L -M
S
N
S
T L -M
S
N
S
T L -M
S
N
S
H
0.007 (0.180)
M
T L -M
S
N
S
C
(NOTE 1) 52
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1 K F VIEW S 0.007 (0.180)
M
J
-T-
SEATING PLANE
VIEW S T L -M
S
T L -M
S
N
S
N
S
NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 -- 0.020 -- 0.025 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 0.020 -- 10 2 0.710 0.730 0.040 --
MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 -- 0.64 -- 19.05 19.20 19.05 19.20 1.07 1.21 1.07 1.21 1.07 1.42 -- 0.50 2 10 18.04 18.54 1.02 --
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM62110 11
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM62110 12
CODELINE TO BE PLACED HERE
*MCM62110/D*
MCM62110/D MOTOROLA FAST SRAM

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